Course Objective:
This course aims at providing a comprehensive knowledge on the
structure and behaviour of computer hardware architecture. Application of design concepts
with combinational or sequential digital systems, including various peripheral devices. It
culminates in realization of the concepts with logical verification in Logisim and various case
studies.
Course Rationale:
The purpose of learning this course is to acquire knowledge about
processor, memory, input / output devices interconnected by bus. It encompasses the
definition of the machine’s instruction set architecture. The course emphasizes instruction set
design, pipelining, memory technology, memory hierarchy, virtual memory management, and
I/O sub systems.
CO : 1
Understand the functionality of the computer, CPU functional units - control unit, memory unit, arithmetic and logic unit instruction execution unit and the interconnections among these
components.
CO : 2
Understand the CPU operations, instruction interpretation and execution Outline the concepts of micro-operations, RTL operations, main memory, cache memory and virtual memory organizations.
CO : 3
Understand the different types of I/O subsystems and I/O transfer techniques.
CO : 4
Understand the design issues of RISC and CISC CPUs and the design issues of pipeline architectures.
